1. Field of the Invention
The present invention relates to a data transmission apparatus which transmits data between a plurality of data processing units, and more specifically to a plurality of information processing modules each of which can function as one computer, and which in combination can be constituted as a versatile computer apparatus and can process in parallel.
2. Description of the Prior Art
There is shown in FIG. 10 an example of a data transmission apparatus between data processing units known in the prior art. Reference numeral 101 designates a bus comprising a control line, an address bus, a data bus or the like, and numerals 110a, 110b bus masters which can control and occupy the bus 101 and can input or output data. In the bus masters 110a, 110b, numerals 111a, 111b designate CPUs, numeral 112a an input/output port to transmit data to outside or receive it from outside, numeral 113a a memory, numerals 114a, 114b bus exchangers, and numerals 115a, 115b buffers. Numerals 130a, 130b designate bus slaves which cannot control and occupy the bus 101 but can input or output data to the bus masters 110a, 110b, and the first bus slave 130a is a system input/output port and the second bus slave 130b is a system memory. Numerals 131, 132 designate parallel and serial input/output ports respectively, numeral 133 a decoder, and numeral 134 a memory.
Operation of the data transmission apparatus will now be described.
The bus master 110a or 110b supplies address of the input/output port 130a or the system memory 130b to the address bus. In the writing operation, data is also supplied to the data bus. And then the bus master 110 generates any command of input/output reading and writing or memory reading and writing onto the command line, and the bus slave 130 corresponding to this responds. That is, the corresponding bus slave 130 takes data during the writing operation and outputs it to the bus during the reading operation. And then the bus slave 130 transmits the transfer recognition signal to the bus master 110, which finishes writing or reading cycle and stops transmission of command on the command line and removes the address and data from the bus; thereby one operation is completed.
Although single bus master 110 produces output in the above description, when one bus master is producing output and other bus master with high priority is intended to produce output, the bus changing is performed by the bus exchanger 114 and the data transfer of the bus master with higher priority may be performed.
In such data transmission apparatus in the prior art, however, when the bus master 110 produces output, the data processing unit at input side being opposite to the bus master 110 must be previously determined by the address bus in order to transmit data. Also when the bus master 110 is at input side, the data processing unit at output side must be previously determined in order to transmit data.
Particularly in a data driven computer, when data are distributed in a plurality of data processing units in sequence from the light loaded data processing units or output data from the plurality of data processing units are collected in a single data processing unit, the system cannot be constituted practically. Furthermore, since the address setting is required at every time of transmission, the data transmission apparatus is unsuitable for high-speed transmission.